The AL110 PC to TV scan converter chip accepts graphic data from PC and Macintosh graphics controllers and converts them into broadcast-quality NTSC or PAL TV signals. In addition to analog RGB data, 24-bit digital RGB data can be input to maintain the best video quality and avoid noise problems. An integrated high-quality anti-flicker filter (SmartFilter (tm)) removes the unpleasant flicker caused by the interlaced display of high contrast graphics while maintaining the original clarity and sharpness of informative data such as natural pictures and text. The chip is fully programmable with I^ (2)C interface. In case I^ (2)C programming is not available, each single control register can also be programmed through VGA sync signals at a slower bit rate. Additional features include four levels of sharpness control using 3-line filter and brightness control. The AL110 is a highly integrated mix-signal chip, packaged in 20mm x 14mm x1.4mm 128-pin LQFP (thin quad flat package). Power-down is achieved by using either hardware or software control. The AL110 is a highly integrated mix-signal chip, packaged in 20mm x 14mm x 14mm 128-pin LQFP (thin quad flat package). Power-down is achieved by using either hardware or software control. The enhanced features and superior quality make the AL110 very suitable for PC video to TV conversion in VGA add-on cards, Internet set-top boxes, or network and laptop PCs. Either analog RGB or digital RGB data can be input to the chip. The analog RGB data is digitized by three 8-bitvideo A/D's and is converted into 24-bit digit RGB data. For graphic controllers with standard or proprietary digital RGB output such as a high-color feature connector, VAFC, or flat panel interface, the optional 24-bit digital RGB interface provides a solution for optional video quality. There is no resolution drop during the A/D or D/A conversion processes or problem introduced in the analog video path or clock recovery circuits, which normally cause headaches for system manufactures. The 24-digital RGB is passed to the digital processing unit of the chip. This DSP unit dose the processing and scan conversion operations such as flicker filtering, YUV filtering, scaling and color space conversion data is sent to the digital TV encoder video data is sent to the digital TV encoder for converting into broadcast quality composite and S-video signals, which are in turn converted by three 9-bit D/A converters into analog outputs. The I^ (2)C interface provides full software programmability. Another option is to control the chip by programming the duty cycle of VGA sync signals at a slower bit-rate. The software programmability also at a slower bit-rate. The software programmability also applies for the power-down feature. Input interface: RGB data and horizontal and vertical sync signals of the VGA controller are used as inputs. Analog RGB data or 24-bit digital RGB data are both supported. The analog R, G, B signals are digitized with three built-in 8-bit A/D converters. The voltage swing of VGA RGB signals is typically 0.7 volts. The VRT and VRB pins set the input voltage references of the A/D converters. When digital RGB data is used as the input, the internal A/D converters can be disabled by setting pin be disabled by setting pin ADEN low; Supported resolutions: The resolutions supported are 64 x 480 for NTSC and 800 x 600 for PAL. A scan rate of 60 Hz is supported for 640 x 480 resolution, and 50 Hz for 800 x 600 resolution; Flicker filter: The scan converter chip performs 3 line flicker filtering to reduce the flicker to reduce the flicker due to interlaced display of high contrast lines. Four levels of flicker select control the sharpness of the picture; Proprietary dynamic filtering (Smartfilter (tm)) is applied to retain the original PC video resolution and sharpness while removing the flickering effect. The hardware intelligently tells which parts of the screen are natural picture or text whose clarity need to be retained. One out of 45 different filters is selected and applied dynamically for each single pixel based on the statistics of its surrounding pixels. The criteria of which filter to choose from is based on a model derived from the ensemble of psychophysical experiments based on human eye responses to the flicker of different picture types; Panning control: Panning control is used to pan the video on the TV screen; Brightness control: Four levels of brightness control; Color bar: Four levels of brightness control; Digital video encoder: The digital video encoder inputs the digital color-space and scan-rate converted video data and output broadcast quality NTSC and PAL signals. The color sub-carrier is generated by an eight times over-sampling clock, which greatly simplifies external analog smoothing filter design. Four times over-sampling mode is also available by either software or hardware pin control. The modulated digital signals are converted to analog levels by three 9-bit D/A converters. Composite and S-video signals are output simultaneously; I^2C interface: Software that runs either on a CPU in the PC or on a micro-controller in a stand-alone system can program the AL110 via these 2-pin ports. Two alternative I^2C device addresses can be selected. Hardware default setting can be overwritten by software; VGA sync programming: The commands for programming the chip is transmitted the VGA sync in the form of a variation of the sync duty cycle using proprietary communication protocols. The chip will detect, error-correct, and decode the incoming data string and set the control registers accordingly. The chip is fully programmable using the VGA sync. The data rate is roughly 50 register-bit writes per second; Packing: The chip is fabricated using CMOS process and packaged in a 20mm x 14mm x 1.44mm 128-pin LQFP package. This packaged type is perfect for PCMCIA or laptop computer applications.
Features
- Convert non-interlaced VGA or Macintosh video into interlaced TV format (NTSC/PAL)
- High integrated design with built-in NTSC/PAL encoder, ADC, DAC, memory
- Broadcast TV quality
- High clarity 3-line anti-flicker filter
- 4 levels of sharpness control
- Horizontal and vertical panning control
- Digital 24-bit RGB/VAFC interface for best quality
- Power down feature controlled by software or hardware
- Full programmability via I^ (2)C interface and/or VGA sync
- Brightness control
- Built-in color bar
- Small LQFP package for PCMCIA or notebook applications
Symbol | Type | Pin | Description |
---|---|---|---|
AB | In (0.7V) | 103 | Analog blue |
AC | Out (1 V p-p) | 35 | Analog chroma output |
ACMP | out (1V p-p) | 40 | Analog composite output |
Aden | In (CMOSd) | 10 | Use internal ADC; 0, use external ADC; 1, use internal ADC |
AG | In (0.7V) | 105 | Analog green |
AR | In (0.7V) | 110 | Analog red |
AY | Out (1V p-p) | 37 | Analog luma output |
Blue | In (CMOSd) | 95-102 | Graphic blue input data |
CLK type | In (CMOSd) | 124 | Clock frequency; 0-28.6 MHz for NTSC, 35.5 MHz for PAL; 1-14.3 MHz for NTSC, 17.7 MHz for PAL |
COMP | In (0.1uF) | 42 | Compensation Pin, 0.1uF pull-up |
GCLK | In (CMOS) | 115 | Graphic pixel clock |
GHSDIV | Out (CMOS) | 118 | Graphic pixel clock divide by M signal for external PLL circuits |
GHSOUT | Out (TTL) | 117 | Graphic hsync output buffered from external VGA HSYNC |
GHSQYNC | IN (CMIOSd) | 112 | Graphic HSYNC |
GREEN | In (CMOSd) | 85-88, 90-93 | Graphic green input data |
GVSOUT | Out (TTL) | 119 | Graphic vsync output buffered from external VGA VSYNC |
GVSYNC | In (CMOSd) | 113 | Graphic VSYNC |
I2C | In (CMOSd) | 14 | I2C bus connected; 0-enable VGA sync programming; 1-enable I2C programming |
I2CADDR | In (CMOSd) | 13 | I2C sub address; 0-write address=88, read adress=89; 1-write address=88, read address=8D |
INTYPE | In (CMOSd) | 128, 1 | Graphic input type; 00-24-bit RGB 01-reserved; 10-feature connector; 11-VAFC |
PAL | In (CMOSd) | 5 | NTSC/PAL select; 0-NTC; 1-PAL |
/PWRDN | In (CMOSd) | 120 | Power down enable (active low) |
Red | In (CMOSd) | 76-83 | Graphic Red input |
/Reset | In (CMOSd) | 121 | Reset (active low) |
RESET | In (62 ohm) | 41 | Full scale current adjust, 62 ohm pull-down |
SCL | In (CMOSsu) | 15 | I2C clock |
SDA | In/out (CMOSsu) | 12 | 12C data |
TIN | In (CMOSd) | 1, 3, 4, 5, 6, 75, 76 | Test pin, connect to GND |
TIN | In (CMOSD) | 17, 18, 19, 21, 22, 23, 25, 26, 27, 29, 30, 31 | Test pin, no connect |
TVCLK | Out (CMOS) | 123 | Clock output for graphic chip clock |
VRB | In (0V) | 108 | Bottom voltage reference |
VREF | In (1.23V) | 33 | Voltage reference input |
VRT | In | 107 | Top voltage reference |
XIN1/FIN1 | In (CMOS) | 3 | Crystal input/external clock input 1for NTSC |
XIN2/FIN2 | In (CMOS) | 126 | Crystal input/external clock input 2 for PAL |
XOUT1 | Out (CMOS) | 2 | Crystal output 1 for NTSC |
XOUT2 | Out (CMOS) | 125 | Crystal output 2 for PAL |
NC | N/A | 39, 46, 47, 49, 50, 52, 54, 55, 57, 59, 63, 65, 66, 67, 68, 70, 72, 74 | No connection |
VDD x 13 | N/A | 11, 24, 45, 53, 58, 64, 71, 75, 89, 116, 122 | Digital power |
GND x 14 | N/A | 16, 20, 28, 48, 51, 56, 60, 69, 73, 94, 114, 127 | Digital ground |
ADGND x 3 | N/A | 106, 109 | ADC ground |
ADVDD x 3 | N/A | 104, 111 | ADC power |
DAGND x 3 | N/A | 34, 36, 38 | DAC ground |
DAVDD x 3 | N/A | 32, 43, 44 | DAC power |
Main Products
digital panel meter